Present-day platform firmware doesn’t use “voodoo” mode as extensively as in the past. Therefore, if the platform firmware CPU operating mode is flat protected mode, it must switch the CPU into that mode. X86/圆4 CPU resets in a modified real mode operating mode, i.e., real mode at physical address FFFF_FFF0h. In this stage, the platform firmware switches the CPU to the platform firmware CPU operating mode it could be real mode, “voodoo” mode, or flat protected mode, depending on the platform firmware. This address is always located in the BIOS/UEFI flash memory on the motherboard. In x86/圆4 this address is 4GB minus 16-bytes ( FFFF_FFF0h). In all platforms, the bootstrap processor (BSP) starts execution by fetching the instruction located in an address known as the reset vector.
You need to have a clear understanding of the boot process before we get into the system address map and bus protocol-related talks. This section explains the boot process in sufficient detail to understand the system address map and other bus protocol-related matters that are explained later in this article. The word “PCI expansion ROM” mostly refers to the ROM chip on a PCI device, except when the context contains other specific explanation.Memory in this context could mean RAM, ROM or other forms of memory which can be addressed by the CPU. The word “memory space” means the set of memory addresses accessible by the CPU, i.e., the memory that is addressable from the CPU.The word “memory range” or “memory address range” means the range, i.e., from the base/start address to the end address (base address + memory size) occupied by a device in the CPU memory space.Flash memory refers to either the chip on the motherboard that stores the BIOS/UEFI or the chip that stores the PCI expansion ROM contents.The word “memory controller” refers to part of the chipset or the CPU that controls the RAM modules and accesses to the RAM modules.The word “main memory” refers to the RAM modules installed on the motherboard.Therefore, this article uses these conventions: It can be confusing for those new to the subject. There are several different usages of the word “memory” in this article. Part 2 of this article will focus on PCIe-based systems. PCIe is virtually the main bus protocol in every x86/圆4 systems today. However, it’s very important to understand how it works in the lowest level in terms of software/firmware, because it’s impossible to understand the later bus protocol, the PCI Express (PCIe) without understanding PCI bus protocol. PCI bus protocol is a legacy bus protocol by today’s standard. This article focuses on systems based on the PCI bus protocol. Therefore, you must understand the address mapping mechanism of the specific bus protocol to understand the system address map initialization. Bus protocol being utilized in a system dictates the address mapping of the memory of a device-that’s attached to the bus-to the system address map. X86/圆4 system address map is complex due to backward compatibility that must be maintained in the bus protocol in x86/圆4 architecture. PCI device memory address mapping is only required if the PCI device contains memory, such as a video card, network card with onboard buffer, or network card that supports PCI expansion ROM, etc. This article explains the initialization of the system address map, focusing on the initialization of the PCI chip registers that control PCI device memory address mapping to the system address map.
Low-level programmers are sometimes puzzled about the mapping of device memory, such as PCI device memory, to the system address map. This article serves as a clarification about the PCI expansion ROM address mapping, which was not sufficiently covered in my “Malicious PCI Expansion ROM” article published by Infosec Institute last year ( /pci-expansion-rom/).